Resistive Memory Cell With Sloped Bottom Electrode

ABSTRACT

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

TECHNICAL FIELD

The present disclosure relates to resistive memory cells, e.g.,conductive bridging random access memory (CBRAM) or resistiverandom-access memory (ReRAM) cells, having a sloped bottom electrode.

BACKGROUND

Resistive memory cells, such as conductive bridging memory (CBRAM) andresistive RAM (ReRAM) cells are a new type of non-volatile memory cellsthat provide scaling and cost advantages over conventional Flash memorycells. A CBRAM is based on the physical re-location of ions within asolid electrolyte. A CBRAM memory cell can be made of two solid metalelectrodes, one relatively inert (e.g., tungsten) the otherelectrochemically active (e.g., silver or copper), separated from eachother by a thin layer or film of non-conducting material. The CBRAM cellgenerates programmable conducting filaments across the non-conductingfilm through the application of a bias voltage across the non-conductingfilm. The conducting filaments may be formed by single or very fewnanometer-scale ions. The non-conducting film may be referred to as anelectrolyte because it provides for the propagation of the conductivefilament(s) across the film through an oxidation/reduction process muchlike in a battery. In a ReRAM cell, the conduction occurs throughcreation of a vacancy chain in an insulator. The generation of theconductive filament(s)/vacancy-chain(s) creates an on-state (highconduction between the electrodes), while the dissolution of theconductive filament(s)/vacancy-chain(s), e.g., by applying a similarpolarity with Joule heating current or an opposite polarity but atsmaller currents, reverts the electrolyte/insulator back to itsnonconductive off-state. In this disclosure both the electrolyte film,layer, or region of a CBRAM cell and the insulator film, layer, orregion of a ReRAM cell are referred to as an “electrolyte,” for the sakeof simplicity.

A wide range of materials have been demonstrated for possible use inresistive memory cells, both for the electrolyte and the electrodes. Oneexample is the Cu/SiOx based cell in which the Cu is the activemetal-source electrode and the SiOx is the electrolyte.

One common problem facing resistive memory cells is the on-stateretention, i.e., the ability of the conductive path (filament or vacancychain) to be stable, especially at the elevated temperatures that thememory parts may typically be qualified to (e.g., 85 C/125 C).

FIG. 1 shows a conventional CBRAM cell 1A, having a top electrode 10(e.g., copper) arranged over a bottom electrode 12 (e.g., tungsten),with the electrolyte or middle electrode 14 (e.g., SiO₂) arrangedbetween the top and bottom electrodes. Conductive filaments 18 propagatefrom the bottom electrode 12 to the top electrode 10 through theelectrolyte 14 when a bias voltage is applied to the cell 1A. Thisstructure has various potential limitations or drawbacks. For example,the effective cross-sectional area for filament formation, which may bereferred to as the “confinement zone” or the “filament formation area”indicated as A_(FF), is relatively large and unconfined, making thefilament formation area susceptible to extrinsic defects. Also,multi-filament root formation may be likely, due to a relatively largearea, which may lead to weaker (less robust) filaments. In general, thelarger the ratio between the diameter or width of the filament formationarea A_(FF) (indicated by “x”) to the filament propagation distance fromthe bottom electrode 12 to the top electrode 10 (in this case, thethickness of the electrolyte 14, indicated by “y”), the greater thechance of multi-root filament formation. Further, a large electrolytearea surrounds the filament, which provides diffusion paths for thefilament and thus may provide poor retention. Thus, restricting thevolume of the electrolyte material in which the conductive path formsmay provide a more robust filament due to spatial confinement. Thevolume of the electrolyte material in which the conductive path formsmay be restricted by reducing the area in contact between the bottomelectrode 12 and the electrolyte 14.

As used herein, “conductive path” refers a conductive filament (e.g., ina CBRAM cell), vacancy chain (e.g., in an oxygen vacancy based ReRAMcell), or any other type of conductive path for connecting theelectrodes of a non-volatile memory cell, typically through anelectrolyte layer or region arranged between the electrodes. As usedherein the “electrolyte layer” or “electrolyte region” refers to anelectrolyte/insulator/memory layer or region between the bottom and topelectrodes through which the conductive path propagates.

FIG. 2 shows certain principles of a CBRAM cell formation. Conductivepaths 18 may form and grow laterally, or branch into multiple parallelpaths. Further, locations of the conductive paths may change with eachprogram/erase cycle. This may contribute to a marginal switchingperformance, variability, high-temp retention issues, and/or switchingendurance. Restricting switching volume has shown to benefit theoperation. These principles apply to ReRAM and CBRAM cells. A keyobstacle for adoption of these technologies is switching uniformity.

FIGS. 3A and 3B show a schematic view and an electron microscope imageof an example known bottom electrode configuration 1B for a CBRAM cell(e.g., having a 1T1R architecture). In this example, the bottomelectrode 12 is a cylindrical via, e.g., a tungsten-filled via with aTi/TiN liner. A top contact and/or anode 20 may be connected to the topelectrode 10 as shown. The bottom electrode 12 may provide a relativelylarge filament formation area A_(FF) of about 30,000 nm², for example,which may lead to one or more of the problems or disadvantages discussedabove.

SUMMARY

Some embodiments provide resistive memory cells, e.g., CBRAM or ReRAMcells, and methods of forming such resistive memory cells, having abottom electrode formed with one or more sloped surfaces that define anupwardly-pointed tip, which may be a point, edge, or surface, dependingon the embodiment. The bottom electrode may have any shape that definesan upwardly-pointed tip. For example, the bottom electrode may have anelongated prism shape with a triangular cross-section that extendsacross one or multiple bottom electrode connections, or a concave bowlshape defining an upwardly-pointed ring-shaped tip edge, or anupwardly-pointed pyramid shape.

When a voltage bias is applied to such resistive memory cell, theupwardly-pointing tip of the bottom electrode may focus the electricfield more precisely than in known cells, which may provide moreconsistent filament formation, thus improving the consistency ofprogramming voltage and cell predictability, e.g., as compared withcertain conventional designs.

According to one embodiment, a method of forming a resistive memory cellcomprises forming a plurality of bottom electrode connections;depositing a bottom electrode layer over the bottom electrodeconnections; performing a first etch to remove portions of the bottomelectrode layer such that the remaining bottom electrode layer definesat least one sloped surface; forming an oxidation layer on each slopedsurface of the remaining bottom electrode layer; performing a secondetch on the remaining bottom electrode layer and oxidation layer on eachsloped surface to define at least one upwardly-pointing bottom electroderegion above each bottom electrode connection, each upwardly-pointingbottom electrode region defining a bottom electrode tip; and forming anelectrolyte region and a top electrode over each bottom electrode tipsuch that the electrolyte region is arranged between the top electrodeand the respective bottom electrode top.

According to another embodiment, a resistive memory cell comprises aplurality of bottom electrode connections; at least one bottom electroderegion formed over and conductively coupled to the bottom electrodeconnections, each bottom electrode region having at least one slopedsidewall and defining an upwardly-pointing tip; an electrolyte regionand a top electrode over each bottom electrode tip such that theelectrolyte region is arranged between the top electrode and therespective bottom electrode top; and a top electrode connectionconductively coupled to each top electrode.

According to another embodiment, a method of forming a resistive memorycell comprises forming a plurality of bottom electrode connections;depositing a bottom electrode layer over the bottom electrodeconnections; performing an etch to remove portions of the bottomelectrode layer to form at least one upwardly-pointing bottom electroderegion above the bottom electrode connections, each upwardly-pointingbottom electrode region defining a bottom electrode tip; and forming anelectrolyte region and a top electrode over each bottom electrode tipsuch that the electrolyte region is arranged between the top electrodeand the respective bottom electrode top.

According to another embodiment, a resistive memory cell comprises aplurality of bottom electrode connections; at least one bottom electroderegion formed over and conductively coupled to the bottom electrodeconnections, each bottom electrode region having at least two slopedsidewalls and defining an upwardly-pointing tip; an electrolyte regionand a top electrode over each bottom electrode tip such that theelectrolyte region is arranged between the top electrode and therespective bottom electrode top; and a top electrode connectionconductively coupled to each top electrode.

BRIEF DESCRIPTION OF THE FIGURES

Example embodiments are discussed below with reference to the drawings,in which:

FIG. 1 shows an example conventional CBRAM cell;

FIG. 2 shows certain principles of CBRAM cell formation;

FIGS. 3A and 3B show a schematic view and an electron microscope imageof an example known CBRAM cell configuration;

FIGS. 4A1-4N2 illustrate an example method for forming a resistivememory cell structure, e.g., a CBRAM or ReRAM cell structure, includingbottom electrodes having a sloped surface defining a pointed upper-edge,according to one embodiment of the present invention;

FIGS. 5A1-5N2 illustrate an another example method for forming aresistive memory cell structure, e.g., a CBRAM or ReRAM cell structure,including sloped ring-shaped bottom electrodes defining a ring-shapedpointed upper-edge, according to one embodiment of the presentinvention;

FIGS. 6A1-6L2 illustrate an another example method for forming aresistive memory cell structure, e.g., a CBRAM or ReRAM cell structure,including bottom electrodes having a pair of sloped side walls defininga pointed upper-edge, according to one embodiment of the presentinvention;

FIGS. 7A1-7K2 illustrate an another example method for forming aresistive memory cell structure, e.g., a CBRAM or ReRAM cell structure,including pyramid shaped bottom electrodes having four sloped sidesmeeting at an upwardly pointed tip, according to one embodiment of thepresent invention; and

FIGS. 8A-8C illustrate an another example method for forming a resistivememory cell structure, e.g., a CBRAM or ReRAM cell structure, includingpyramid shaped bottom electrodes having three sloped sides meeting at anupwardly pointed tip, according to one embodiment of the presentinvention.

DETAILED DESCRIPTION

As discussed above, embodiments of the present invention may provideresistive memory cells, e.g., CBRAM or ReRAM cells, and methods offorming such resistive memory cells, having a bottom electrode formedwith one or more sloped surfaces that define an upwardly-pointed tip,e.g., a triangular shaped bottom electrode, a concave bowl-shaped bottomelectrode with a ring-shaped tip edge, or a pyramid shaped bottomelectrode. In operation, the upwardly-pointed tip of the bottomelectrode may focus the electric field and provide a reduced filamentformation area A_(FF), which may provide more consistent filamentformation, thus improving the consistency of programming voltage andcell predictability, e.g., as compared with certain conventionaldesigns.

FIGS. 4A1-4N2 illustrate an example method for forming a resistivememory cell structure, e.g., a CBRAM or ReRAM cell structure, includingbottom electrodes having a sloped surface defining a pointed upper-edge,according to one embodiment of the present invention.

As shown in FIG. 4A1 (cross-sectional side view) and FIG. 4A2 (topview), an array of bottom electrode connectors 102 are formed in asubstrate 100. Bottom electrode connectors 102 and substrate 100 may beformed in any suitable manner (e.g., using conventional semiconductorfabrication techniques) and from any suitable materials. For example,substrate 100 may be formed from an insulator, e.g., SiO₂, and eachbottom electrode connector 102 may have a conductor region 104 formedfrom copper (Cu) or other conductive material, and a connection region106 formed from tungsten (W) or other suitable material. In thisexample, each bottom electrode connector 102 is formed with a circularvia-type shape. However, each bottom electrode connector 102 may beformed with any other suitable shape, e.g., an elongated line orelongated rectangular shape, a square shape, etc.

Next, as shown in FIG. 4B1 (cross-sectional side view) and FIG. 4B2 (topview), a bottom electrode (or cathode) layer 110 and a hard mask 112 aredeposited or formed over the substrate 100 and bottom electrodeconnectors 102. Bottom electrode layer 110 may comprise any suitableconductive material or materials, e.g., polysilicon, doped polysilicon,amorphous silicon, doped amorphous silicon, or any other suitablematerial, and may be deposited or formed in any suitable manner. Hardmask layer 112 may be formed from any suitable materials (e.g., SiN,SiON, or other dielectric material) and may be deposited or formed inany suitable manner as known in the art.

Next, as shown in FIG. 4C1 (cross-sectional side view) and FIG. 4C2 (topview), the hard mask 112 is patterned, e.g., by forming and patterning aphotoresist layer 116 over the hard mask 112, using any suitablephotolithography techniques. As shown, the photoresist layer 116 ispatterned with openings 118 that expose particular areas of theunderlying hard mask 112. In this embodiment, openings 118 are formed aselongated trenches extending between or alongside rows of underlyingbottom electrode connectors 102, as shown in FIG. 4C2. However, openings118 may alternatively be formed with any other shape, e.g., circularvia-type openings, and/or may correspond with underlying bottomelectrode connectors 102 in a one-to-one manner (as opposed to theillustrated one-to-multiple arrangement). Also, in the illustratedembodiment, the openings 118 are located such that each underlyingbottom electrode connector 102 has a single corresponding opening wall120 overlying that bottom electrode connector 102, wherein the singlecorresponding opening wall 120 for bottom electrode connector 102provides the basis for a single sloped bottom electrode sidewall formedover that bottom electrode connector 102 according to the followingprocess steps. In particular, opening wall 120A overlies bottomelectrode connector 102A, opening wall 120B overlies bottom electrodeconnector 102B, and opening wall 120C overlies bottom electrodeconnector 102C. In other embodiments, the openings 118 are shaped and/orlocated such that multiple opening walls 120 overly each bottomelectrode connector 102, e.g., such that multiple sloped bottomelectrode sidewalls may be formed over each bottom electrode connector102.

Next, as shown in FIG. 4D1 (cross-sectional side view) and FIG. 4D2 (topview), etch and strip/removal processes are performed to transfer thephotoresist pattern into the hard mask 112 and remove the remainingphotoresist, thereby forming a patterned hard mask 112 having an arrayof openings 124.

Next, bottom electrode layer 110 may be etched through the openings 124in the patterned hard mask 112 using any suitable isotropic etchprocess. FIGS. 4E1-4G2 illustrate a progression of the etch process, inparticular showing “snapshots” of the structure at three differentpoints in time along the progression of the etch. Thus, FIGS. 4E1 and4E2 show a snapshot at a first instant in time during the etch; FIGS.4F1 and 4F2 show a snapshot at a second instant in time during the etch;and FIGS. 4G1 and 4G2 show a snapshot at or after completion of theetch. As shown in these figures, the etch process may continue to removematerial from bottom electrode layer 110 until the remaining portions ofthe bottom electrode layer 110 define a sloped sidewall surface 130above each bottom electrode connector 102. In some embodiments, the etchprocess may separate bottom electrode layer 110 into discrete bottomelectrode layer regions, e.g., regions 110A and 110B shown in FIGS. 4G1and 4G2.

Next, as shown in FIG. 4H1 (cross-sectional side view) and FIG. 4H2 (topview), the exposed sloped sidewall surfaces 130 of bottom electrodelayer regions 110A and 110B are oxidized using any suitable process, toform an oxidized layer 134 on each sloped region 130.

Next, as shown in FIG. 411 (cross-sectional side view) and FIG. 412 (topview), the hard mask 112 is removed using any suitable process, e.g., byetching or stripping.

Next, as shown in FIG. 4J1 (cross-sectional side view) and FIG. 4J2 (topview), the bottom electrode layer regions 110A and 110B are etchedutilizing the oxidized regions as a hardmask to block the etching ofbottom electrode underneath. And the oxidized layers 134 are removed,thereby forming discrete bottom electrodes 140, each having anupwardly-pointing region defining a sloped side wall surface 142 and atip 144. The etch and oxide removal process may be performed in twosteps, e.g., using a highly selective etch that preserves the oxidelayers 134 and then gently removing the oxide layers 134 in a subsequentstep, or alternatively may be performed in a single step, e.g., using aslightly higher oxide etch rate that removes the oxide layers 134 alongwith portions of the bottom electrode layer material.

Next, as shown in FIG. 4K1 (cross-sectional side view) and FIG. 4K2 (topview), an insulator or electrolyte layer 150 and a top electrode (anode)layer 152 are formed over the stack, and in particular, over each bottomelectrode 140. Electrolyte layer 150 may comprise any suitabledielectric or memristive type material or materials, for example,SiO_(x) (e.g., SiO₂), GeS, CuS, TaO_(x), TiO₂, Ge₂Sb₂Te₅, GdO, HfO, CuO,Al₂O₃, or any other suitable material. Top electrode layer 152 maycomprise any suitable conductive material or materials, e.g., Ag, Al,Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may bedeposited or formed in any suitable manner.

Next, as shown in FIG. 4L1 (cross-sectional side view) and FIG. 4L2 (topview), the electrolyte layer 150 and top electrode layer 152 arepatterned by forming and patterning a photoresist layer 160 over the topelectrode layer 152, using any suitable photolithography techniques. Asshown, the photoresist layer 160 is patterned with openings 162 thatexpose particular areas of the top electrode layer 152. In thisembodiment, openings 162 are formed as elongated trenches betweenadjacent rows of bottom electrodes 140, as shown in FIG. 4L2. However,photoresist layer 160 may be patterned in any other suitable manner. Forexample, photoresist layer 160 may be patterned such that a discretephotoresist region remains over each bottom electrode 140 (rather thanspanning multiple bottom electrodes 140 as shown in FIG. 4L2).

Next, as shown in FIG. 4M1 (cross-sectional side view) and FIG. 4M2 (topview), etch and strip/removal processes are performed to transfer thephotoresist pattern into the electrolyte layer 150 and top electrodelayer 152 and remove the remaining photoresist, thereby dividing theelectrolyte layer 150 and top electrode layer 152 into discreteelectrolyte regions 170 and corresponding top electrodes 172. As shownin FIG. 4M2, each electrolyte region 170/top electrode 172 forms a rowspanning multiple bottom electrodes 140.

Next, as shown in FIG. 4N1 (cross-sectional side view) and FIG. 4N2 (topview), top electrode interconnects 180 may be formed in an insulatormaterial 182 deposited over the stack, using any suitable techniques.The insulator material 182 may comprise any suitable insulator (e.g.,SiO₂), which may or may not be the same material as substrate 100. Topelectrode interconnects 180 may be formed from any suitable conductor(e.g., Cu), and may be formed at any suitable locations relative to topelectrodes 172. In the illustrated example, as shown in FIG. 4N2, a topelectrode interconnect 180 is formed over each elongated top electrode172 at the end of each column (i.e., the connection may be periodicrather than over each bitcell).

In this manner, an array of resistive memory cells is formed, in whichthe bottom electrode 140 has an upwardly-pointing region defining asloped side wall 142 and a pointed tip 144. In operation, conductivefilament propagation from each respective bottom electrode 140 issubstantially confined to the pointed tip 144, as the electric fieldnaturally concentrates at the point, edge, or surface having thesmallest radius of curvature. Thus, the sharper the point of tip 144,the greater the concentration of the filament-generating electric field,and thus the smaller the effective filament formation area A_(FF). Thus,the pointed tip shaped bottom electrode 140 may provide a substantiallyreduced effective filament formation area A_(FF), as compared withconventional bottom electrode structures.

FIGS. 5A1-5N2 illustrate an example method for forming a resistivememory cell structure, e.g., a CBRAM or ReRAM cell structure, includingsloped ring-shaped bottom electrodes defining a ring-shaped pointedupper-edge, according to one embodiment of the present invention.

As shown in FIG. 5A1 (cross-sectional side view) and FIG. 5A2 (topview), an array of bottom electrode connectors 202 are formed in asubstrate 200. Bottom electrode connectors 202 and substrate 200 may beformed in any suitable manner (e.g., using conventional semiconductorfabrication techniques) and from any suitable materials. For example,substrate 200 may be formed from an insulator, e.g., SiO₂, and eachbottom electrode connector 202 may have a conductor region 204 formedfrom copper (Cu) or other conductive material, and a connection region206 formed from tungsten (W) or other suitable material. In thisexample, each bottom electrode connector 202 is formed with a circularvia-type shape. However, each bottom electrode connector 202 may beformed with any other suitable shape, e.g., an elongated line orelongated rectangular shape, a square shape, etc.

Next, as shown in FIG. 5B1 (cross-sectional side view) and FIG. 5B2 (topview), a bottom electrode (or cathode) layer 210 and a hard mask 212 aredeposited or formed over the substrate 200 and bottom electrodeconnectors 202. Bottom electrode layer 210 may comprise any suitableconductive material or materials, e.g., polysilicon, doped polysilicon,amorphous silicon, doped amorphous silicon, or any other suitablematerial, and may be deposited or formed in any suitable manner. Hardmask layer 212 may be formed from any suitable materials (e.g., SiN,SiON, or other dielectric material) and may be deposited or formed inany suitable manner as known in the art.

Next, as shown in FIG. 5C1 (cross-sectional side view) and FIG. 5C2 (topview), the hard mask 212 is patterned, e.g., by forming and patterning aphotoresist layer 216 over the hard mask 212, using any suitablephotolithography techniques. As shown, the photoresist layer 216 ispatterned with openings 218 that expose particular areas of theunderlying hard mask 212. In this embodiment, openings 218 are formed ascircular openings over each bottom electrode connector 202, with theperimeter of each circular opening 218 being smaller than and alignedconcentrically within the perimeter of the respective bottom electrodeconnector 202, as shown in FIG. 5C2. In other embodiments, circularopenings 218 may align in an overlapping manner with respect to theirrespective bottom electrode connectors 202, as viewed from the top view.

Next, as shown in FIG. 5D1 (cross-sectional side view) and FIG. 5D2 (topview), an etch is performed to transfer the photoresist pattern into thehard mask 212, thereby forming a patterned hard mask 212 having an arrayof openings 224. Then, as shown in FIG. 5E1 (cross-sectional side view)and FIG. 5E2 (top view), the remaining photoresist is removed, e.g., bystripping or other suitable process.

Next, bottom electrode layer 210 may be etched through the openings 224in the patterned hard mask 212 using any suitable isotropic etchprocess. FIGS. 5F1 and 5F2 illustrate a snapshot of the structure at aninstant during the etch process, and FIGS. 5G1 and 5G2 show a snapshotat or after completion of the etch. As shown in these figures, the etchprocess may remove material from bottom electrode layer 210 until theremaining portions of the bottom electrode layer 210 define a concave,bowl-shaped structure having a sloped U-shaped (in the cross-sectionalside view), ring-shaped (in the top view) sidewall 230 above each bottomelectrode connector 202. In some embodiments, the etch process may etchfully through the bottom electrode layer 210 and down to the bottomelectrode connection region 206 to expose a top surface area ofconnection region 206, e.g., at the bottom center of the etched area. Inother embodiments, the etch process may not extend fully through thebottom electrode layer 210, such that a portion of the bottom electrodematerial 210 remains over the top surface of connection region 206, evenat the bottom center of the etched area.

Next, as shown in FIG. 5H1 (cross-sectional side view) and FIG. 5H2 (topview), the exposed sloped U-shaped (side view), ring-shaped (top view)sidewalls 230 defined in bottom electrode layer 210 are oxidized usingany suitable process, to form an oxidized layer 234 on each slopedregion 230.

Next, as shown in FIG. 5I1 (cross-sectional side view) and FIG. 512 (topview), hard mask 212 is removed using any suitable process, e.g., byetching or stripping.

Next, as shown in FIG. 5J1 (cross-sectional side view) and FIG. 5J2 (topview), the remaining bottom electrode layer 210 is etched utilizing theoxidized regions as a hardmask to block the etching of bottom electrodeunderneath. And the oxidized layers 234 are removed, thereby forming adiscrete bottom electrode 240 over each bottom electrode connection 206.As shown, each bottom electrode 240 comprises a concave, bowl-shapedstructure having a sloped U-shaped (cross-sectional side view),ring-shaped (in the top view) sidewall surface 242 and anupwardly-pointed ring-shaped tip 244. The etch and oxide removal processmay be performed in two steps, e.g., using a highly selective etch thatpreserves the oxide layers 234 and then gently removing the oxide layers234 in a subsequent step, or alternatively may be performed in a singlestep, e.g., using a slightly higher oxide etch rate that removes theoxide layers 234 along with portions of the bottom electrode layermaterial.

In some embodiments, each bottom electrode 240 may have an centralopening that exposes a top surface area of the underlying connectionregion 206. In other embodiments, a portion of the bottom electrodematerial 210 remains over the top surface of connection region 206, evenat the bottom center of the bowl-shaped structure, such that the topsurface of the underlying connection region 206 is not exposed throughthe center of the bottom electrode 240.

Next, as shown in FIG. 5K1 (cross-sectional side view) and FIG. 5K2 (topview), an insulator or electrolyte layer 250 and a top electrode (anode)layer 252 are formed over the stack, and in particular, over each bottomelectrode 240. Electrolyte layer 250 may comprise any suitabledielectric or memristive type material or materials, for example,SiO_(x) (e.g., SiO₂), GeS, CuS, TaO_(x), TiO₂, Ge₂Sb₂Te₅, GdO, HfO, CuO,Al₂O₃, or any other suitable material. Top electrode layer 252 maycomprise any suitable conductive material or materials, e.g., Ag, Al,Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may bedeposited or formed in any suitable manner.

Next, the electrolyte layer 250 and top electrode layer 252 arepatterned and etched to divide the electrolyte layer 250 and topelectrode layer 252 into discrete electrolyte 270/top electrode 272regions, each covering one or multiple bottom electrodes 202. In theexample shown in FIG. 5L1 (cross-sectional side view) and FIG. 5L2 (topview), the electrolyte layer 250 and top electrode layer 252 arepatterned and etched to form a discrete electrolyte 270/top electrode272 region over each individual bottom electrode 202. (In an alternativeembodiment shown in FIGS. 5N1 and 5N2 (discussed below), the electrolytelayer 250 and top electrode layer 252 are patterned and etched to formelongated electrolyte 270/top electrode 272 regions, each spanning a rowof multiple bottom electrodes 202.)

Next, as shown in FIG. 5M1 (cross-sectional side view) and FIG. 5M2 (topview), top electrode interconnects 280 may be formed in an insulatormaterial 282 deposited over the stack, using any suitable techniques.The insulator material 282 may comprise any suitable insulator (e.g.,SiO₂), which may or may not be the same material as substrate 200. Topelectrode interconnects 280 may be formed from any suitable conductor(e.g., Cu), and may be formed at any suitable locations relative to topelectrodes 272. In this example embodiment, as shown in FIG. 5M2, adiscrete top electrode interconnect 280 is formed over each topelectrode 272.

FIG. 5N1 (cross-sectional side view) and FIG. 5N2 (top view) illustratean alternative embodiment in which the electrolyte layer 250 and topelectrode layer 252 are formed as elongated electrolyte 270/topelectrode 272 regions, each spanning a row of multiple bottom electrodes202. A top electrode interconnect 280 is formed over and connected toeach elongated top electrode 272, at the end of each column (i.e., theconnection may be periodic rather than over each bitcell), as shown inFIG. 5N2.

In the manner shown in FIGS. 5A1-5N2, an array of resistive memory cellsis formed, in which each bottom electrode 240 has a concave bowl-shapedstructure defining an upwardly-pointed ring-shaped tip 244. Inoperation, conductive filament propagation from each respective bottomelectrode 240 is substantially confined to the ring-shaped pointed tip244, as the electric field naturally concentrates at the point, edge, orsurface having the smallest radius of curvature. Thus, the sharper thepoint of ring-shaped tip 244, the greater the concentration of thefilament-generating electric field, and thus the smaller the effectivefilament formation area A_(FF). Thus, the ring-shaped pointed tip ofeach bottom electrode 240 may provide a substantially reduced effectivefilament formation area A_(FF), as compared with conventional bottomelectrode structures.

FIGS. 6A1-6L2 illustrate an example method for forming a resistivememory cell structure, e.g., a CBRAM or ReRAM cell structure, includingbottom electrodes having a pair of sloped side walls defining a pointedupper-edge, according to one embodiment of the present invention.

As shown in FIG. 6A1 (cross-sectional side view) and FIG. 6A2 (topview), an array of bottom electrode connectors 302 are formed in asubstrate 300. Bottom electrode connectors 302 and substrate 300 may beformed in any suitable manner (e.g., using conventional semiconductorfabrication techniques) and from any suitable materials. For example,substrate 300 may be formed from an insulator, e.g., SiO₂, and eachbottom electrode connector 302 may have a conductor region 304 formedfrom copper (Cu) or other conductive material, and a connection region306 formed from tungsten (W) or other suitable material. In thisexample, each bottom electrode connector 302 is formed with a circularvia-type shape. However, each bottom electrode connector 302 may beformed with any other suitable shape, e.g., an elongated line orelongated rectangular shape, a square shape, etc.

Next, as shown in FIG. 6B1 (cross-sectional side view) and FIG. 6B2 (topview), a bottom electrode (or cathode) layer 310 and a hard mask 312 aredeposited or formed over the substrate 300 and bottom electrodeconnectors 302. Bottom electrode layer 310 may comprise any suitableconductive material or materials, e.g., polysilicon, doped polysilicon,amorphous silicon, doped amorphous silicon, or any other suitablematerial, and may be deposited or formed in any suitable manner. Hardmask layer 312 may be formed from any suitable materials (e.g., SiN,SiON, or other dielectric material) and may be deposited or formed inany suitable manner as known in the art.

Next, as shown in FIG. 6C1 (cross-sectional side view) and FIG. 6C2 (topview), the hard mask 312 is patterned, e.g., by forming and patterning aphotoresist layer 316 over the hard mask 312, using any suitablephotolithography techniques. As shown, the photoresist layer 316 ispatterned with openings 318 that expose particular areas of theunderlying hard mask 312. In this embodiment, openings 318 are formed aselongated trenches extending between adjacent rows of underlying bottomelectrode connectors 302, as shown in FIG. 6C2. However, openings 318may alternatively be formed with any other shape, e.g., circularvia-type openings, and/or may correspond with underlying bottomelectrode connectors 302 in a one-to-one manner (as opposed to theillustrated one-to-multiple arrangement).

Next, as shown in FIG. 6D1 (cross-sectional side view) and FIG. 6D2 (topview), etch and strip/removal processes are performed to transfer thephotoresist pattern into the hard mask 312 and remove the remainingphotoresist, thereby forming a patterned hard mask 312 having an arrayof openings 324.

Next, bottom electrode layer 310 may be etched through the openings 324in the patterned hard mask 312 using any suitable isotropic etchprocess. FIGS. 6E1-6G2 illustrate a progression of the etch process, inparticular showing “snapshots” of the structure at three differentpoints in time along the progression of the etch. Thus, FIGS. 6E1 and6E2 show a snapshot at a first instant in time during the etch; FIGS.6F1 and 6F2 show a snapshot at a second instant in time during the etch;and FIGS. 6G1 and 6G2 show a snapshot at or after completion of theetch. As shown in these figures, the etch process may remove materialfrom bottom electrode layer 310 until the remaining portions of thebottom electrode layer 310 define elongated bottom electrode regions310A, 310B, and 310C above respective rows of bottom electrodeconnectors 302, each bottom electrode region 310A, 310B, and 310C havinga pair of sloped sidewalls 330 meeting at an upwardly-pointing edge tip332, thus defining a triangular cross-sectional shape. As used herein,triangular means three sided, wherein each side may be linear or may benon-linear (e.g., curved, irregular, or otherwise non-linear).

Next, as shown in FIG. 6H1 (cross-sectional side view) and FIG. 6H2 (topview), the hard mask 312 is removed using any suitable process, e.g., byetching or stripping, leaving a series of bottom electrodes 340(corresponding to bottom electrode regions 310A, 310B, and 310C).

Next, as shown in FIG. 611 (cross-sectional side view) and FIG. 612 (topview), an insulator or electrolyte layer 350 and a top electrode (anode)layer 352 are formed over the stack, and in particular, over each bottomelectrode 340. Electrolyte layer 350 may comprise any suitabledielectric or memristive type material or materials, for example,SiO_(x) (e.g., SiO₂), GeS, CuS, TaO_(x), TiO₂, Ge₂Sb₂Te₅, GdO, HfO, CuO,Al₂O₃, or any other suitable material. Top electrode layer 352 maycomprise any suitable conductive material or materials, e.g., Ag, Al,Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may bedeposited or formed in any suitable manner.

Next, as shown in FIG. 6J1 (cross-sectional side view) and FIG. 6J2 (topview), the electrolyte layer 350 and top electrode layer 352 arepatterned by forming and patterning a photoresist layer 360 over the topelectrode layer 352, using any suitable photolithography techniques. Asshown, the photoresist layer 360 is patterned with openings 362 thatexpose particular areas of the top electrode layer 352. In thisembodiment, openings 362 are formed as elongated trenches betweenadjacent rows of bottom electrodes 340, as shown in FIG. 6J2. However,photoresist layer 360 may be patterned in any other suitable manner. Forexample, photoresist layer 360 may be patterned such that a discretephotoresist region remains over each bottom electrode 340 (rather thanspanning multiple bottom electrodes 340 as shown in FIG. 6J2).

Next, as shown in FIG. 6K1 (cross-sectional side view) and FIG. 6K2 (topview), etch and strip/removal processes are performed to transfer thephotoresist pattern into the electrolyte layer 350 and top electrodelayer 352 and remove the remaining photoresist, thereby dividing theelectrolyte layer 350 and top electrode layer 352 into discreteelectrolyte regions 370 and corresponding top electrodes 372. As shownin FIG. 6K2, each electrolyte region 370/top electrode 372 forms a rowspanning multiple bottom electrodes 340.

Next, as shown in FIG. 6L1 (cross-sectional side view) and FIG. 6L2 (topview), top electrode interconnects 380 may be formed in an insulatormaterial 382 deposited over the stack, using any suitable techniques.The insulator material 382 may comprise any suitable insulator (e.g.,SiO₂), which may or may not be the same material as substrate 300. Topelectrode interconnects 380 may be formed from any suitable conductor(e.g., Cu), and may be formed at any suitable locations relative to topelectrodes 372. In the illustrated example, as shown in FIG. 6L2, a topelectrode interconnect 380 is formed over each elongated top electrode372 at the end of each column (i.e., the connection may be periodicrather than over each bitcell).

In this manner, an array of resistive memory cells is formed, in whicheach bottom electrode 340 has an upwardly-pointing triangularcross-section defining a pair of sloped side walls 330 meeting at apointed tip 332. In operation, conductive filament propagation from eachrespective bottom electrode 340 is substantially confined to the pointedtip 332, as the electric field naturally concentrates at the point,edge, or surface having the smallest radius of curvature. Thus, thesharper the point of tip 332, the greater the concentration of thefilament-generating electric field, and thus the smaller the effectivefilament formation area A_(FF). Thus, the generally triangular, pointedtip shaped bottom electrode 340 may provide a substantially reducedeffective filament formation area A_(FF), as compared with conventionalbottom electrode structures.

FIGS. 7A1-7K2 illustrate an example method for forming a resistivememory cell structure, e.g., a CBRAM or ReRAM cell structure, includingpyramid shaped bottom electrodes having four sloped sides meeting at anupwardly pointed tip, according to one embodiment of the presentinvention.

As shown in FIG. 7A1 (cross-sectional side view) and FIG. 7A2 (topview), an array of bottom electrode connectors 402 are formed in asubstrate 400. Bottom electrode connectors 402 and substrate 400 may beformed in any suitable manner (e.g., using conventional semiconductorfabrication techniques) and from any suitable materials. For example,substrate 400 may be formed from an insulator, e.g., SiO₂, and eachbottom electrode connector 402 may have a conductor region 404 formedfrom copper (Cu) or other conductive material, and a connection region406 formed from tungsten (W) or other suitable material. In thisexample, each bottom electrode connector 402 is formed with a circularvia-type shape. However, each bottom electrode connector 402 may beformed with any other suitable shape, e.g., an elongated line orelongated rectangular shape, a square shape, etc.

Next, as shown in FIG. 7B1 (cross-sectional side view) and FIG. 7B2 (topview), a bottom electrode (or cathode) layer 410 is deposited or formedover the substrate 400 and bottom electrode connectors 402. Bottomelectrode layer 410 may comprise any suitable conductive material ormaterials, e.g., polysilicon, doped polysilicon, amorphous silicon,doped amorphous silicon, or any other suitable material, and may bedeposited or formed in any suitable manner.

Next, as shown in FIG. 7C1 (cross-sectional side view) and FIG. 7C2 (topview), a patterned hard mask layer 412 is formed over the bottomelectrode layer 410. Hard mask layer 412 may be formed from any suitablematerials (e.g., SiN, SiON, or other dielectric material), and patternedin any suitable manner known in the art. For example, hard mask layer412 may be patterned using a photoresist layer and suitable patterningand etch process. In the illustrated embodiment, hard mask layer 412 ispatterned with a two-dimensional array of circular openings 424 locatedin the areas between (i.e., not overlying) the underlying bottomelectrode connection regions 406. However, it should be understood thatin other embodiments, openings 424 may alternatively be formed with anyother shape, e.g., elongated trench-type openings, and/or may bepartially or fully located above underlying bottom electrode connectionregions 406.

Next, bottom electrode layer 410 may be etched through the openings 424in the patterned hard mask 412 using any suitable etch process.

FIGS. 7D1-7F2 illustrate a progression of the etch process, inparticular showing “snapshots” of the structure at three differentpoints in time along the progression of the etch. Thus, FIGS. 7D 1 and7D2 show a snapshot at a first instant in time during the etch; FIGS.7E1 and 7E2 show a snapshot at a second instant in time during the etch;and FIGS. 7F1 and 7F2 show a snapshot at or after completion of theetch. As shown in these figures, the etch process may remove materialfrom bottom electrode layer 410 until the remaining portions of thebottom electrode layer 410 define a two-dimensional array of pyramidshaped bottom electrodes 440, each located above a respective bottomelectrode connector 402. Each pyramid shaped bottom electrode 440 hasfour sloped sidewalls 430 meeting at an upwardly-pointing tip 432.

As used herein, pyramid means a three-dimensional shape having three ormore triangular or generally triangular outer sides that meet at a pointor relatively small edge or surface, and a base having a trilateral,quadrilateral, or any other polygon shape. Each generally triangularouter side may be planar or non-planar (e.g., concave, convex,irregular, or otherwise non-planar).

In one embodiment, the four sloped sidewalls 430 of each pyramid shapedbottom electrode 440 are triangular or generally triangular and concaveor generally concave, due to the etch process that form the pyramidshapes.

Next, as shown in FIG. 7G1 (cross-sectional side view) and FIG. 7G2 (topview), the hard mask 412 is removed using any suitable process, e.g., byetching or stripping, leaving the two-dimensional array ofpyramid-shaped bottom electrodes 440.

Thus, the patterning hard mask layer 412 with the two-dimensional arrayof openings shown in FIGS. 7C1 and 7C2 provides for a two-dimensionalarray of pyramid-shaped bottom electrodes, one per bottom electrodeconnection 406, as opposed to patterning the hard mask with elongatedtrench openings that lead to elongated bottom electrodes, as disclosedin the example steps shown in FIGS. 6C1-6H2 discussed above.

Next, as shown in FIG. 7H1 (cross-sectional side view) and FIG. 7H2 (topview), an insulator or electrolyte layer 450 and a top electrode (anode)layer 452 are formed over the stack, and in particular, over each bottomelectrode 440. Electrolyte layer 450 may comprise any suitabledielectric or memristive type material or materials, for example,SiO_(x) (e.g., SiO₂), GeS, CuS, TaO_(x), TiO₂, Ge₂Sb₂Te₅, GdO, HfO, CuO,Al₂O₃, or any other suitable material. Top electrode layer 452 maycomprise any suitable conductive material or materials, e.g., Ag, Al,Cu, Ta, TaN, Ti, TiN, Al, W or any other suitable material, and may bedeposited or formed in any suitable manner.

Next, as shown in FIG. 711 (cross-sectional side view) and FIG. 712 (topview), the electrolyte layer 450 and top electrode layer 452 arepatterned by forming and patterning a photoresist layer 460 over the topelectrode layer 452, using any suitable photolithography techniques. Asshown, the photoresist layer 460 is patterned with openings 462 thatexpose particular areas of the top electrode layer 452. In thisembodiment, openings 462 are formed as elongated trenches betweenadjacent rows of bottom electrodes 440, as shown in FIG. 712. However,photoresist layer 460 may be patterned in any other suitable manner. Forexample, photoresist layer 460 may be patterned such that a discretephotoresist region remains over each bottom electrode 440 (rather thanspanning multiple bottom electrodes 440 as shown in FIG. 712).

Next, as shown in FIG. 7J1 (cross-sectional side view) and FIG. 7J2 (topview), etch and strip/removal processes are performed to transfer thephotoresist pattern into the electrolyte layer 450 and top electrodelayer 452 and remove the remaining photoresist, thereby dividing theelectrolyte layer 450 and top electrode layer 452 into discreteelectrolyte regions 470 and corresponding top electrodes 472. As shownin FIG. 7J2, each electrolyte region 470/top electrode 472 forms a rowspanning multiple bottom electrodes 440.

Next, as shown in FIG. 7K1 (cross-sectional side view) and FIG. 7K2 (topview), top electrode interconnects 480 may be formed in an insulatormaterial 482 deposited over the stack, using any suitable techniques.The insulator material 482 may comprise any suitable insulator (e.g.,SiO₂), which may or may not be the same material as substrate 400. Topelectrode interconnects 480 may be formed from any suitable conductor(e.g., Cu), and may be formed at any suitable locations relative to topelectrodes 472. In the illustrated example, as shown in FIG. 7K2, a topelectrode interconnect 480 is formed over each elongated top electrode472 at the end of each column (i.e., the connection may be periodicrather than over each bitcell).

In this manner, an array of resistive memory cells is formed, in whicheach bottom electrode 440 has an upwardly-pointing pyramid shape havefour sloped side walls 430 meeting at a pointed tip 432. In operation,conductive filament propagation from each respective bottom electrode440 is substantially confined to the pointed pyramid tip 432, as theelectric field naturally concentrates at the point, edge, or surfacehaving the smallest radius of curvature. Thus, the sharper the point ofthe pyramid tip 432, the greater the concentration of thefilament-generating electric field, and thus the smaller the effectivefilament formation area A_(FF). Thus, the generally triangular, pointedtip shaped bottom electrode 440 may provide a substantially reducedeffective filament formation area A_(FF), as compared with conventionalbottom electrode structures.

FIGS. 8A-8C illustrate steps in an example method for forming aresistive memory cell structure, e.g., a CBRAM or ReRAM cell structure,including pyramid shaped bottom electrodes having three sloped sidesmeeting at an upwardly pointed tip, according to one embodiment of thepresent invention.

FIG. 8A is a top view of a two-dimensional pattern of bottom electrodeconnections 506 formed in an insulator 500, e.g., analogous to the viewsshown in FIGS. 4A2, 5A2, 6A2, and 7A2. As shown, bottom electrodeconnections 506 are arranged in staggered rows that form a hexagonalpattern, as opposed to the aligned n rows by m columns patterns shown inFIGS. 4A2, 5A2, 6A2, and 7A2.

FIG. 8B is a top view of a patterned hard mask layer 512 formed over abottom electrode layer 510 deposited over bottom electrode connectionregions 506, e.g., analogous to the views shown in FIGS. 4D2, 5E2, 6D2,and 7C2. As shown, mask layer 512 is patterned with a two-dimensionalarray of circular openings 524 located in the areas between (i.e., notoverlying) the underlying bottom electrode connection regions 506.

Finally, FIG. 8C is a top view of a two-dimensional pattern of bottomelectrodes 540 formed by etching the bottom electrode layer 510 throughthe two-dimensional array of circular openings 524 shown in FIG. 8B, andthen removing the hard mask 512, e.g., in a manner similar to theexample embodiments discussed above. The extent of etching through eachhard mask openings 524 is shown in FIG. 8C by a large circle 536. Theportions of the bottom electrode layer 510 remaining after the etchprocess define an array of pyramid shaped bottom electrodes 540, e.g.,similar to the pyramid shaped bottom electrodes 440 formed by the stepsshow in FIGS. 7B1 to 7G2, described above. However, unlike the pyramidshaped bottom electrodes 440, pyramid shaped bottom electrode 540 shownin FIG. 8C have three sloped sides instead of four, due to thearrangement of openings 524 in patterned hard mask layer 512. That is,each pyramid shaped bottom electrode 540 has three sloped side wallsmeeting at an upwardly pointed tip 532. In one embodiment, the threesloped sidewalls of each pyramid shaped bottom electrode 540 aretriangular or generally triangular and concave or generally concave, dueto the etch process that form the pyramid shapes.

Using a hexagonal array as shown in FIGS. 8A-8C may allow for a moredense packing of the resulting bitcells, e.g., by reducing the arrayarea for a particular number of bitcells by a factor of (√3)/2 (i.e.,about 13%), as compared with a rectangular “n×m” array.

As with the pointed bottom electrodes discussed above, conductivefilament propagation from each bottom electrode 540 is substantiallyconfined to the pointed pyramid tip 532, as the electric field naturallyconcentrates at the point, edge, or surface having the smallest radiusof curvature. Thus, the generally triangular, pointed tip shaped bottomelectrode 540 may provide a substantially reduced effective filamentformation area A_(FF), as compared with conventional bottom electrodestructures.

Although the disclosed embodiments are described in detail in thepresent disclosure, it should be understood that various changes,substitutions and alterations can be made to the embodiments withoutdeparting from their spirit and scope.

1-13. (canceled)
 14. A resistive memory cell, comprising: a plurality ofbottom electrode connections; at least one bottom electrode regionformed over and conductively coupled to the bottom electrodeconnections, each bottom electrode region having at least two slopedsidewalls and defining an upwardly-pointing tip; an electrolyte regionand a top electrode over each bottom electrode tip such that theelectrolyte region is arranged between the top electrode and therespective bottom electrode top; and a top electrode connectionconductively coupled to each top electrode.
 15. The resistive memorycell of claim 14, wherein each bottom electrode region extends over andis conductively coupled to multiple bottom electrode connections. 16.The resistive memory cell of claim 14, wherein each bottom electroderegion is aligned with and conductively coupled to a single bottomelectrode connection.
 17. The resistive memory cell of claim 14, whereineach upwardly-pointing bottom electrode region is an elongated regionhaving a pair of sloped sidewalls that meet at a pointed tip edge anddefine a triangular cross-sectional shape.
 18. The resistive memory cellof claim 14, wherein each upwardly-pointing bottom electrode regioncomprises a pyramid shape.
 19. The resistive memory cell of claim 14,wherein each pyramid shaped bottom electrode region has three slopedsidewalls.
 20. The resistive memory cell of claim 14, wherein eachpyramid shaped bottom electrode region has four sloped sidewalls.
 21. Aresistive memory cell, comprising: a plurality of bottom electrodeconnections electrically separated from each other within a substrate; abottom electrode layer over the bottom electrode connections andsubstrate; wherein portions of the bottom electrode layer are removed toform a plurality of bottom electrodes, each bottom electrode havingfirst and second sidewalls forming at least one upwardly-pointing bottomelectrode region above the bottom electrode connections, eachupwardly-pointing bottom electrode region defining a bottom electrodetip; an electrolyte layer deposited directly on the plurality of bottomelectrodes and the substrate wherein said electrolyte layer is patternedsuch that an electrolyte region is formed directly on each bottomelectrode tip and directly on its associated first and second sidewall;and a top electrode over said electrolyte region.
 22. The resistivememory cell of claim 21, wherein the electrolyte region formed on eachbottom electrode tip is configured to provide a path for the formationof a conductive filament or vacancy chain from the bottom electrode tipto the respective top electrode, via the electrolyte region, when avoltage bias is applied to the resistive memory cell.
 23. The resistivememory cell of claim 21, wherein the resistive memory cell is aconductive bridging memory (CBRAM) cell.
 24. The resistive memory cellof claim 21, wherein the resistive memory cell is a resistive RAM(ReRAM) cell.
 25. The resistive memory cell of claim 21, wherein: the atleast one upwardly-pointing bottom electrode region comprises at leastone elongated bottom electrode region that extends over and isconductively connected to multiple bottom electrode connections.
 26. Theresistive memory cell of claim 25, wherein said first and secondsidewalls are a pair of sloped sidewalls that meet at a pointed tip edgeand define a triangular cross-sectional shape.
 27. The resistive memorycell of claim 21, wherein each upwardly-pointing bottom electrode regionis pyramid shaped.
 28. The resistive memory cell of claim 27, whereineach pyramid shaped bottom electrode region has three sloped sidewalls.29. The resistive memory cell of claim 27, wherein each pyramid shapedbottom electrode region has four sloped sidewalls.
 30. The resistivememory cell of claim 21, wherein each upwardly-pointing bottom electroderegion is aligned with and conductively connected to a single bottomelectrode connection.
 31. The resistive memory cell of claim 21,comprising a two-dimensional array of bottom electrode connections; anda two-dimensional array of pyramid shaped bottom electrode regions, eachconductively coupled to one of the bottom electrode connections.
 32. Theresistive memory cell of claim 31, comprising a plurality of elongatedelectrolyte regions and corresponding elongated top electrodes, eachelongated electrolyte region and corresponding elongated top electrodecovering a row of multiple pyramid shaped bottom electrode regions.